Considerations for Delay and Sum Beamformer on a Multi-Core Processor

Authors

  • M. Prakash Narayanan NPOL, DRDO
  • G. Vijay Gopal NPOL, DRDO
  • R. Rajesh NPOL, DRDO

DOI:

https://doi.org/10.3849/aimt.01994

Keywords:

sonar beamformer, multicore processing, sonar signal processing

Abstract

This paper presents a real-time, scalable beamformer solution utilizing Intel multicore processors for a Passive Surveillance Sonar (PSS) system. With larger arrays being developed to address the complexities of the ocean environment, the demand to handle high-bandwidth data in the beamformer has become essential. The time-domain delay-and-sum beamformer is analyzed for a cylindrical array, and the best configuration is selected for a simplified realization. The beamformer is demanding in terms of both computation and memory. Considerations for developing an optimized implementation on a multicore machine are discussed, along with the realization of a scalable solution. The beamformer is evaluated for performance with arrays of varying complexities and successfully meets real-time requirements. Finally, a solution for a PSS with a panoramic 450-beam configuration, which has evolved based on this concept, demonstrates the capabilities of the proposed approach.

Author Biographies

  • M. Prakash Narayanan, NPOL, DRDO

    Signal Processing, NPOL

  • G. Vijay Gopal, NPOL, DRDO

    Scientist, Signal processing division, NPOL

  • R. Rajesh, NPOL, DRDO

    Opto-electronics division, NPOL

References

BELL, T.G. Probing the Ocean for Submarines. Bloomington: Peninsula Publishing, 2011. ISBN 0-932146-26-0.

TIAN, H., S. GUO, P. ZHAO, M. GONG and C. SHEN. Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP. Sensors, 2021, 21(4), 1425. https://doi.org/10.3390/s21041425.

KLILOU, A., S. BELKOUCH, P. ELLEAUME, P.L. GALL, F. BOURZEIX and M.M. HASSANI. Real-Time Parallel Implementation of Pulse-Doppler Radar Signal Processing Chain on a Massively Parallel Machine Based on Multi-Core DSP and a Serial RapidIO Interconnect. EURASIP Journal on Advances in Signal Processing, 2014, 2014, 161. https://doi.org/10.1186/1687-6180-2014-161.

WANG, J. and K. LIU. High Frequency Active Sonar Real-time Signal Processing System Based on FPGA. In: IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC). Qingdao: IEEE, 2018. https://doi.org/10.1109/ICSPCC.2018.8567799.

GEORGE, A.D., J. MARKWELL and R. FOGARTY. Real-Time Sonar Beamform-Ing on High-Performance Distributed Computers. Parallel Computing, 2000, 26(9), pp. 1231-1252. https://doi.org/10.1016/S0167-8191(00)00037-5.

ALLEN, G.E. and B.L. EVANS. Real Time Sonar Beamforming on Workstations Using Process Networks and POSIX Threads. IEEE Transactions on Signal Processing, 2000, 48(3), pp. 921-926. https://doi.org/10.1109/78.824694.

SAROFEEN, C and P. GILLETT. A High Performance Parallel and Heterogeneous Approach to Narrowband Beamforming. IEEE Transactions on Parallel and DIs-tributed Systems, 2016, 27(8), pp. 2196-2207. https://doi.org/10.1109/TPDS.2015.2494038.

NARAYANAN, M.P., G.V. GOPAL and R. RAJESH. Accelerating Performance of a Real-Time 2D Delay-Sum Beamformer on General Purpose Processors. In: IEEE International Symposium on Ocean Technology (SYMPOL). Kochi: IEEE, 2021. https://doi.org/10.1109/SYMPOL53555.2021.9689448.

NARAYANAN, M.P., G.V. GOPAL and R. RAJESH. Design and Implementation Considerations for a 3D Beamformer on State-of-the-Art Multicore Processors. In: IEEE OCEANS 2022. Chennai: IEEE, 2022, pp. 1-7. https://doi.org/10.1109/OCEANSChennai45887.2022.9775501.

JAECKEL, O. Strengths and Weaknesses of Calculating Beamforming in the Time Domain. In: 1st Berlin Beamforming Conference. Berlin: BeBeC, 2006.

MARTINEZ-NIETO, D. et al. Digital Signal Processing on Intel Architecture. Intel Technology Journal, 2009, 13(1), pp. 122-145. ISSN 1535-864X.

NARAYANAN, M.P., G. VIJAYGOPAL, and R. RAJESH. A High-Performance Parallel Approach to Delay Sum Beamformer in a Homogeneous Multicore Environment. Defense Science Journal, 2024, 74(5), pp. 755-762. https://doi.org/10.14429/dsj.74.19505.

Downloads

Published

11-12-2025

Issue

Section

Original research article

Categories

How to Cite

Prakash Narayanan, M. (2025). Considerations for Delay and Sum Beamformer on a Multi-Core Processor. Advances in Military Technology, 20(2), 565-576. https://doi.org/10.3849/aimt.01994

Similar Articles

1-10 of 51

You may also start an advanced similarity search for this article.

Most read articles by the same author(s)